Student: /* John's Papers */

2015-11-24T22:28:30Z

John's Papers

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[[Image:John_Backes.jpg|200px]]

==About John==

I completed my Ph.D. under [[Marc Riedel | Prof. Marc Riedel]] in 2013. My research pertained to logic synthesis, technology mapping, SAT-based algorithms, and model checking. I am now a Senior Research Scientist at [http://www.rockwellcollins.com/ Rockwell Collins]

== John's Papers ==

'''Dissertation'''

{|
| rowspan=2 |
{| style="background:#F0E68C"
|- valign=top
| width="100" | '''title''':
| width="500" | [[Media:Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pdf |Algorithms and Data Structures For Logic Synthesis And Verification Using Boolean Satisfiability]]
|-
| '''author''':
| [[John Backes]]
|-
| '''Dissertation''':
| Ph.D., [http://www.ece.umn.edu Electrical and Computer Engineering], [http://www.umn.edu University of Minnesota], 2013.
|}
| align=center width="70" |
[http://www.mriedel.ece.umn.edu/wiki/images/9/96/Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]
 [[Media:Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pdf | Paper]]
| align=center width="70" |
[http://www.mriedel.ece.umn.edu/wiki/images/f/fa/Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pptx http://cctbio.ece.umn.edu/wiki/images/3/36/Ppt.jpg]
 [http://www.mriedel.ece.umn.edu/wiki/images/f/fa/Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pptx Slides]
|}

'''Journal Papers'''

{|
| rowspan=2 |
{| style="background:#F0E68C"
|- valign=top
| width="100" | '''title''':
| width="500" | [[Media:Backes_Riedel_The_Synthesis_of_Cyclic_Dependencies_with_Boolean_Satisfiability.pdf‎ | The Synthesis of Cyclic Dependencies with Boolean Satisfiability]]
|-
| '''authors''':
| [[John Backes]] and [[Marc Riedel]]
|-
| '''appeared in''':
| [http://todaes.acm.org/ ACM Transactions on Design Automation of Electronic Systems], 2012.
|}
| align=center |
[http://www.mriedel.ece.umn.edu/wiki/images/d/df/Backes_Riedel_The_Synthesis_of_Cyclic_Dependencies_with_Boolean_Satisfiability.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]
 [[Media:Backes_Riedel_The_Synthesis_of_Cyclic_Dependencies_with_Boolean_Satisfiability.pdf‎ | Paper]]
|}

{|
|
{| style="background:#F0E68C"
|- valign="top"
| width="100" | '''title''':
| width="500" | [[Media:Qian_Backes_Riedel_The_Synthesis_of_Stochastic_Circuits_for_Nanoscale_Computation_IJNMC.pdf | The Synthesis of Stochastic Circuits for Nanoscale Computation]]
|- valign="top"
| '''authors''':
| [[Weikang Qian]], [[John Backes]], and [[Marc Riedel]]
|- valign="top"
| '''appeared in''':
| [http://www.igi-global.com/Bookstore/TitleDetails.aspx?TitleId=1117&DetailsType=Description International Journal of Nanotechnology and Molecular Computation], vol. 1, no. 4, pp. 39–57, 2010.
|}
| align=center width="70 |
[http://cctbio.ece.umn.edu/wiki/images/a/a8/Qian_Backes_Riedel_The_Synthesis_of_Stochastic_Circuits_for_Nanoscale_Computation_IJNMC.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]
 [[Media:Qian_Backes_Riedel_The_Synthesis_of_Stochastic_Circuits_for_Nanoscale_Computation_IJNMC.pdf | Paper]]
|}

'''Conference Papers'''

{|

| rowspan=2 |
{| style="background:#F0E68C"
|- valign=top
| width="100" | '''title''':
| width="500" | [[Media:Backes_Riedel_Using_Cubes_of_Non-State_Variables_With_Property_Directed_Reachability.pdf‎ ‎‎‎ | Using Cubes of Non-state Variables With Property Directed Reachability]]
|-
| '''authors''':
| [[John Backes]] and [[Marc Riedel]]
|-
| '''presented at''':
| [http://www.date-conference.com/ Design Automation & Test in Europe], Grenoble, France, 2013.
|}
| align=center width="70" |
[http://www.mriedel.ece.umn.edu/wiki/images/c/c0/Backes_Riedel_Using_Cubes_of_Non-State_Variables_With_Property_Directed_Reachability.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]
 [[Media:Backes_Riedel_Using_Cubes_of_Non-State_Variables_With_Property_Directed_Reachability.pdf‎ | Paper]]
| align=center width="70" |
[http://www.mriedel.ece.umn.edu/wiki/images/4/41/Backes_Riedel_Using_Cubes_of_Non-State_Variables_With_Property_Directed_Reachability.pptx http://cctbio.ece.umn.edu/wiki/images/3/36/Ppt.jpg]
 [http://www.mriedel.ece.umn.edu/wiki/images/4/41/Backes_Riedel_Using_Cubes_of_Non-State_Variables_With_Property_Directed_Reachability.pptx Poster]

|}

{|

| rowspan=2 |
{| style="background:#F0E68C"
|- valign=top
| width="100" | '''title''':
| width="500" | [[Media:Backes_Riedel_Resolution_Proofs_As_A_Data_Structure_For_Logic_Synthesis.pdf‎‎‎ | Resolution Proofs as a Data Structure For Logic Synthesis]]
|-
| '''authors''':
| [[John Backes]] and [[Marc Riedel]]
|-
| '''presented at''':
| [http://iwls.org/ The International Workshop on Logic Synthesis], La Jolla, CA, 2011.
|}
| align=center width="70" |
[http://www.mriedel.ece.umn.edu/wiki/images/2/27/Backes_Riedel_Resolution_Proofs_As_A_Data_Structure_For_Logic_Synthesis.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]
 [[Media:Backes_Riedel_Resolution_Proofs_As_A_Data_Structure_For_Logic_Synthesis.pdf | Paper]]
| align=center width="70" |
[http://www.mriedel.ece.umn.edu/wiki/images/5/5e/Iwls2011final_final.ppt http://cctbio.ece.umn.edu/wiki/images/3/36/Ppt.jpg]
 [http://cctbio.ece.umn.edu/wiki/images/f/f1/Backes_Riedel_Resolution_Proofs_as_a_Data_Structure_for_Logic_Synthesis.ppt Slides]

|}

{|
|
{| style="background:#F0E68C"
|- valign="top"
| width="100" | '''title''':
| width="500" | [[Media:Backes_Riedel_Reduction_Of_Interpolants_For_Logic_Synthesis.pdf‎‎ | Reduction of Interpolants For Logic Synthesis]]
|- valign="top"
| '''authors''':
| [[John Backes]] and [[Marc Riedel]]
|- valign="top"
| '''presented at''':
| [http://www.iccad.com The International Conference on Computer-Aided Design], San Jose, CA, 2010.
|}
| align=center width="70" |
[http://cadbio.com/wiki/images/b/b6/Backes_Riedel_Reduction_Of_Interpolants_For_Logic_Synthesis.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]
 [[Media:Backes_Riedel_Reduction_Of_Interpolants_For_Logic_Synthesis.pdf | Paper]]
| align=center width="70" |
[http://cctbio.ece.umn.edu/wiki/images/0/00/Backes_Riedel_Reduction_Of_Interpolants_For_Logic_Synthesis.ppt http://cctbio.ece.umn.edu/wiki/images/3/36/Ppt.jpg]
 [http://cctbio.ece.umn.edu/wiki/images/0/00/Backes_Riedel_Reduction_Of_Interpolants_For_Logic_Synthesis.ppt Slides]
|}
{|
|
{| style="background:#F0E68C"
|- valign="top"
| width="100" | '''title''':
| width="500" | [[Media:Backes_Riedel_The_Synthesis_of_Cyclic_Dependencies_with_Craig_Interpolation.pdf‎ | The Synthesis of Cyclic Dependencies with Craig Interpolation]]
|- valign="top"
| '''authors''':
| [[John Backes]] and [[Marc Riedel]]
|- valign="top"
| '''presented at''':
| [http://www.sigda.org/iwls/iwls2009 The International Workshop on Logic and Synthesis], Berkeley, CA, 2009.
|}
| align=center width="70" |
[http://cctbio.ece.umn.edu/wiki/images/e/ec/Backes_Riedel_The_Synthesis_of_Cyclic_Dependencies_with_Craig_Interpolation.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]
 [[Media:Backes_Riedel_The_Synthesis_of_Cyclic_Dependencies_with_Craig_Interpolation.pdf‎ | Paper]]
| align=center width="70" |
[http://www.mriedel.ece.umn.edu/wiki/images/a/ad/Backes_Riedel_The_Synthesis_Of_Functional_Dependencies_With_Craig_Interpolation.ppt http://cctbio.ece.umn.edu/wiki/images/3/36/Ppt.jpg]
 [http://www.mriedel.ece.umn.edu/wiki/images/a/ad/Backes_Riedel_The_Synthesis_Of_Functional_Dependencies_With_Craig_Interpolation.ppt Slides]
|}
{|
|
{| style="background:#F0E68C"
|- valign="top"
| width="100" | '''title''':
| width="500" | [[Media:Backes_Riedel_The_Analysis_of_Cyclic_Circuits_With_Boolean_Satisfiability.pdf | The Analysis of Cyclic Circuits with Boolean Satisfiability]]
|- valign="top"
| '''authors''':
| [[John Backes]], [[Brian Fett]], and [[Marc Riedel]]
|- valign="top"
| '''presented at''':
| [http://www.iccad.com/events/eventdetails.aspx?id=86-2-B The International Conference on Computer-Aided Design], San Jose, CA, 2008.
|}
| align=center width="70" |
[http://cctbio.ece.umn.edu/wiki/images/8/84/Backes_Riedel_The_Analysis_of_Cyclic_Circuits_With_Boolean_Satisfiability.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]
 [[Media:Backes_Riedel_The_Analysis_of_Cyclic_Circuits_With_Boolean_Satisfiability.pdf | Paper]]
| align=center width="70" |
[http://cctbio.ece.umn.edu/files/Backes_Riedel_The_Analysis_of_Cyclic_Circuits_With_Boolean_Satisfiability.ppt http://cctbio.ece.umn.edu/wiki/images/3/36/Ppt.jpg]
 [http://cctbio.ece.umn.edu/files/Backes_Riedel_The_Analysis_of_Cyclic_Circuits_With_Boolean_Satisfiability.ppt Slides]
|}

== Contact Information ==

* '''Email''': [[Image:BackesEmail.gif]]
* '''Phone''': (952) 239-7828

John Backes - Revision history

Student: /* John's Papers */